init.c

As with all files, rename the file, adding a preceding l (the letter after k and before m)

line# action
1 replace #include "includes.h" with #include "lincludes.h"
3 remove unsigned int __swi(0x15) inst_fn(int except, unsigned long user_fn);
176 insert rtl_irqstate_t state; after int sv;
201 insert outw_p(ASSERT_MASTER_RESET,GPRESET); after /* Initialize the GP2021 chip in preparation for normal operation. */
201 insert outw_p(DEASSERT_MASTER_RESET,GPRESET); after last insert
201 insert rtl_no_interrupts(state); after last insert
202 replace outpw(SYSTEM_CONFIG,WATCHDOG_OFF); with outw_p(WATCHDOG_OFF,TR(SYSTEM_CONFIG));
203 replace outpw(SYSTEM_SET_UP,UNMASK_INTERRUPT); with outw_p(ENABLE_INTERRUPTS,TR(SYSTEM_SET_UP));
210 replace outw_p(0x11DA, TR(PROG_ACCUM_INT)); with outpw(PROG_ACCUM_INT,0x1416);
211 replaceoutpw(RESET_CONTROL,ALL_CHANNELS); with outw_p(ALL_CHANNELS,TR(RESET_CONTROL));
221 insert rtl_restore_interrupts(state); after InterruptsInOneSecond = (unsigned long)(1.0/900.0e-6);
239 replace ConfigureInterrupt function contents with with rtl_irqstate_t state;

int Base_IO_Port = IO_Address; /* The board base i/o port number. */
int Interrupt_Number = IRQ_Number; /* The board interrupt number. */

/* Some Initializations */

CORRELATOR = Base_IO_Port; /* Global for correlator address. */
GPIMASK = CORRELATOR+4; /* Global for interrupt mask. */
GPRESET = CORRELATOR+6; /* Global for reset. */
GPINT = Interrupt_Number; /* Global for interrupt number.*/

/* Set up the PC's interrupt system to enable GP2021 correlator
interrupts at the highest priority. */

rtl_no_interrupts(state);

rtl_request_irq(GPINT,GPISR);

rtl_restore_interrupts(state);

return;
244 insert /************************************************************************
* Function void HardwareTest(void)
*
************************************************************************/

void HardwareTest(void){

int channel; /* Channel loop counter. */
unsigned cycle_count[MAXCHANNELS]; /* Carrier cycle count. */
unsigned short testdata; /* Used to load the carrier cycle count registers. */
unsigned long interrupt_count; /* Number of interrupts counted. */

int i; /* used for waiting interrupt */

InitialiseGP2021();

outw_p(UNMASK_INTERRUPT,GPIMASK);

rtl_hard_enable_irq (GPINT);

/* Do the interrupt count test */

rtl_printf("\n\nInterrupt Check.\n");

GPIntCtr = interrupt_count = 0;

for (i=1;i<=100;i++) /* Wait for ~100 miliseconds. */
{
udelay(1000);
}

interrupt_count = GPIntCtr;

if(interrupt_count<80 || interrupt_count>150)
{
rtl_printf("\n\nInterrupt count error.");
rtl_printf("\n%lu interrupts were counted - there should have been"
" ~112.",interrupt_count);
rtl_printf("\nCheck the values contained in GPSBLDR2.CFG with the board " "settings.\n\n");
}

else
{
rtl_printf("\n\nInterrupt test passed.");
rtl_printf("\n%lu interrupts were counted - there should have been"
" ~112.\n\n",interrupt_count);
}


rtl_printf("\n\nAddress and Data Bus Interface Check.\n\n");

WaitForFullTIC();

/* Load the carrier DCOs with zero for all DCOs. */

outw_p(0x0000,TR(ALL_CARRIER_DCO_INCR_HIGH));
outw_p(0x0000,TR(ALL_CARRIER_DCO_INCR_LOW));;

outw_p(0x0008,TR(TEST_CONTROL)); /* Put the correlator in TM Test mode. */

/* Load the carrier cycle counters (low) alternatively with testdata and
not testdata. */
testdata = 0xAAAA;
for(channel=0;channel {
outw_p(testdata,TR(CH00_CARRIER_CYCLE_COUNTER + 0x0008*channel));
testdata = ~testdata;
}

WaitForFullTIC();

/* Now read CHx_CARRIER_CYCLE_COUNTER_LOW and check equivalence to
testdata or not testdata as appropriate. */

for(channel=0;channel {
cycle_count[channel] =
inw_p(TR(CH00_CARRIER_CYCLE_COUNTER + 0x0008*channel));
}

testdata = 0xAAAA;
for(channel=0;channel {
if( cycle_count[channel] != testdata)
{
rtl_printf("\nAddress/Data bus error for channel %2.2d. ", channel+1);
rtl_printf("Addr:%2.2X Read: %4.4X Should be: %4.4X",
CH00_CARRIER_CYCLE_COUNTER + 0x0008*channel,
cycle_count[channel],testdata);
rtl_printf("\nCheck the values contained in GPSBLDR2.CFG with the " "board settings.\n");
outw_p(MASK_INTERRUPT,GPIMASK); /* Mask interrupts. */
/* QuitGpsBuilder(); */
return;
} else
{
rtl_printf("\nAddress/Data bus test passed for channel %2.2d.", channel+1);
rtl_printf(" Read: %4.4X Should be: %4.4X",cycle_count[channel], testdata);
}

testdata = ~testdata;
}

WaitForFullTIC();

/* Load the carrier cycle counters (low) alternatively with testdata and not testdata. */

testdata = 0x5555;
for(channel=0;channel {
outw_p(testdata,TR(CH00_CARRIER_CYCLE_COUNTER + 0x0008*channel));
testdata = ~testdata;
}

WaitForFullTIC();

/* Now read CHx_CARRIER_CYCLE_COUNTER_LOW and check
equivalence to testdata or not testdata as appropriate. */

for(channel=0;channel { cycle_count[channel] =
inw_p(TR(CH00_CARRIER_CYCLE_COUNTER + 0x0008*channel));
}

testdata = 0x5555;
for(channel=0;channel {
if( cycle_count[channel] != testdata)
{
rtl_printf("\nAddress/Data bus error for channel %2.2d. ",
channel+1);
rtl_printf("Addr:%2.2X Read: %4.4X Should be: %4.4X",
CH00_CARRIER_CYCLE_COUNTER + 0x0008*channel,
cycle_count[channel],testdata);
rtl_printf("\nCheck the values contained in GPSBLDR2.CFG with the "
"board settings.\n");
outw_p(MASK_INTERRUPT,GPIMASK); /* Mask interrupts. */
/* QuitGpsBuilder(); */
return;
}
else
{
rtl_printf("\nAddress/Data bus test passed for channel %2.2d.",
channel+1);
rtl_printf(" Read: %4.4X Should be: %4.4X",cycle_count[channel],
testdata);
}
testdata = ~testdata;
}

rtl_printf("\n OK End of Hardware Test\n");
}

/***************************************************************************
*
* Function: void InterfaceTestInterruptRoutine(void)
*
* Called as an alternative to SVTRACK when running the interface check.
* ACCUM_STATUS_A needs to be read to reset each interrupt.
*
* Input: None.
*
* Output: None.
*
* Return Value: None.
****************************************************************************/
void InterfaceTestInterruptRoutine(void)
{
short accum_status_a;

accum_status_a = inw_p(TR(ACCUM_STATUS_A));
// outb_p(0x20,0xA0); /* Nonspecific EOI for PC PIC B */ // outb_p(0x20,0x20); /* Nonspecific EOI for PC PIC A */
return;
}

/***************************************************************************
*
* Function: void WaitForFullTIC(void)
*
* Waits for a full TIC to occur.
*
* Input: None.
*
* Output: None.
*
* Return Value: None.
****************************************************************************/
void WaitForFullTIC(void)
{
long dropout; /* Stops lock-up if no TICs detected. */

unsigned long oldGPIntCtr; /* The old interrupt count. */
/* Wait for the TIC */

dropout = 0;
inw_p(TR(ACCUM_STATUS_B));

GPIntCtr = oldGPIntCtr = 0;

for(;;)
{

while(GPIntCtr==oldGPIntCtr) /* Wait for a interrupt. */
udelay(1); /* a small delay (1us) is required */


oldGPIntCtr = GPIntCtr;

if((inw_p(TR(ACCUM_STATUS_B))&0x2000) == 0x2000 ) /* test for TIC */
{
TICcount++;
break;
}
else
{
dropout++;
if(dropout>300000L)
{
rtl_printf("\n\nAddress/Data bus error. No TICs were detected.");
rtl_printf("\nCheck the values contained in GPSBLDR2.CFG with the "
"board settings.\n");
/* QuitGpsBuilder(); */
break;
}
}
}
}